PLL problems on K2 #5061

[M. P. Haynes]

I posted a note last night and have also sent one to service @elecraft
but have not had a response from either.  I am missing the clock signal
SCK in the PLL circuitry.  It is also missing on the Control Board.  The
signal sit at level high with no pulses.  I am assuming that this signal
should be there at all times to clock the PLL corrections.  Would someone
with a working K2 or more knowledge of the circuitry give me a reply?
The manual, though very good, does not go into great detail as to how the
circuit works, only what it does.

Thanks in advance.

Pat Haynes-K4BEH
[phone]
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[Don Wilhelm-3]

Pat,

SCK will not be present at all times, if you see some pulses when the VFO is
moved, that is sufficient information that it is working.  The data to the
PLL DAC is only required to be updated when the VFO is changed, not
continuously.  Those clock pulses are hard to see on a 'scope - they are
quite narrow, so try several times.

You said your problem is that the PLL 'will not lock', and I don't
understand specifically what you are referring to.  Are you looking at the
voltage at the left end of R30?  If so, that is a whole different
consideration - and could be caused by something wrong with the VFO
varactors, T5, L30 or the VFO range Selection.

Do you obtain the correct frequency range for the PLL test?  If not, look to
the thermistor board for your problem, a solder bridge is the most usual
problem.

If you have a problem obtaining the proper voltage at the left end of R30,
look at T5 (proper windings, good tinning and well soldered leads).  If you
can change the frequency with L30, you may want to check the actual
frequency present at the lower band edges and compare it with the chart on
the Schematic Key sheet in the manual.

73,
Don W3FPR

> -----Original Message-----
>
> I posted a note last night and have also sent one to service @elecraft
> but have not had a response from either.  I am missing the clock signal
> SCK in the PLL circuitry.  It is also missing on the Control Board.  The
> signal sit at level high with no pulses.  I am assuming that this signal
> should be there at all times to clock the PLL corrections.  Would someone
> with a working K2 or more knowledge of the circuitry give me a reply?
> The manual, though very good, does not go into great detail as to how the
> circuit works, only what it does.
>

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